{"content_id":"htuvoxtoaw","slug":"memory-centric-ai-chips-hbm-hbf-packaging","locale":"en","schema_type":"TechArticle","category":"trends","category_name":"Trends","title":"From GPU-Centric to Memory-Centric: A Shift in the AI Chip Paradigm","summary":"The bottleneck in AI systems is shifting from computational performance alone to the ability to store and move data. As HBM, NAND-based HBF, custom base dies, 3D packaging, and optical interconnects converge, memory-centric computing that co-designs accelerators and memory is gaining traction.","sponsorship_disclosure":null,"author":{"name":"Injoys Editorial Team","url":"https://injoys.com/ko/about"},"key_points":["Memory-centric computing is not about eliminating GPUs, but about co-designing processors and memory hierarchies to reduce the cost of moving data.","Long contexts and more concurrent requests increase KV cache capacity requirements, making total memory capacity and memory hierarchy technologies as important as HBM bandwidth.","HBF leverages the high density of NAND flash, but latency, write endurance, and error management issues make it more likely to complement HBM than replace it outright.","Vertically stacking memory above or below a GPU shortens interconnect distances but creates new constraints involving thermal density, yield, power delivery, and cooling.","Custom HBM expands memory companies' participation in design, but it does not eliminate memory price volatility or supply cycles themselves."],"content_markdown":"The competitive criteria for AI semiconductors are expanding beyond simple computation counts to **how much data can be stored and moved using little power**. In large-scale AI inference, GPUs may sit idle not because they cannot perform computations, but because they do not receive the required model weights and KV cache in time.\n\nThis change is often described as a “shift from GPU-centric to memory-centric computing.” However, this does not mean that GPUs are disappearing or have stopped advancing. More precisely, it is a move toward jointly designing GPUs, HBM, external memory, storage, networking, and software as a single data movement system.\n\n## What Is Memory-Centric Computing?\n\n**Memory-centric computing is an approach that takes memory location, bandwidth, capacity, and computing capabilities as the starting point of system design to reduce the cost of repeatedly moving data to processors.**\n\nThe arithmetic throughput of AI chips has increased rapidly, but retrieving data from outside the chip remains relatively slow and consumes significant power. As a result, the following technologies are becoming important together.\n\n- HBM placed close to a GPU or AI accelerator\n- 3D packaging that vertically connects memory and logic\n- Customized HBM that incorporates control or limited computing functions into the base die\n- Memory expansion and pooling using CXL\n- The HBF concept, which connects NAND flash through a wide interface\n- Optical interconnects intended to reduce transmission power between chips and servers\n- PIM and near-memory computing, which process data close to memory\n\nIn other words, memory-centric computing does not refer to a single memory product. It is a system principle that combines multiple tiers, from fast memory to high-capacity storage, to minimize data movement.\n\n## Why AI Inference Intensifies the Memory Bottleneck\n\n### Model Weights and the KV Cache Create Different Burdens\n\nThe memory required for AI inference can broadly be divided into model weights, activations generated during execution, and the KV cache. Model weights occupy a fixed amount of space even when there are no requests, while the KV cache grows according to input length, output length, and the number of concurrent requests.\n\nTo avoid recomputing previous tokens from scratch each time, transformer models store attention key and value information for each layer in the KV cache. In simplified terms, the KV cache size for a single request is proportional to the following factors.\n\nThe exact KV cache size must be verified from the model architecture and implementation specifications.\n\nThe KV cache stores keys and values separately. Therefore, as context grows longer or more users are processed simultaneously, the KV cache grows rapidly. Not every model uses millions of tokens, nor does cache size uniformly increase by hundreds of times, but it is clear that long-context inference and agentic tasks increase memory pressure.\n\n### Hallucinations and Memory Capacity Are Not the Same Problem\n\nLonger context and retrieval-augmented generation can provide models with more supporting evidence. However, increasing memory alone does not eliminate hallucinations. The quality of search results, prompt design, the model’s reasoning capabilities, source verification, and evaluation frameworks are also necessary.\n\n### Software Can Reduce Physical Memory Demand\n\nThe KV cache bottleneck is not solved solely by adding hardware.\n\n- MQA and GQA reduce the number of KV heads that must be stored.\n- Quantization reduces the number of bytes used by weights and caches.\n- PagedAttention manages caches in pages, mitigating fragmentation and waste.\n- Continuous batching efficiently groups multiple requests.\n- Prefix caching reuses repeated system prompts or shared context.\n- Cache eviction and tiered offloading move less important information to slower memory.\n\nTherefore, the actual amount of memory investment in a data center depends not only on model size but also on the efficiency of the inference engine.\n\n## The Memory Hierarchy of AI Data Centers\n\nIt is difficult for a single type of memory to satisfy speed, capacity, cost, and power efficiency requirements all at once. AI data centers are likely to evolve into the following hierarchy.\n\n| Tier | Representative Technologies | Strengths | Main Limitations | Expected Role |\n|---|---|---|---|---|\n| On-chip | SRAM, registers | Shortest latency | Very limited capacity and high area cost | Immediately needed data and intermediate computation results |\n| Adjacent to accelerator | HBM | High bandwidth and relatively short latency | Capacity, packaging cost, and thermal constraints | Active weights and frequently used KV cache |\n| Server memory | DDR, CXL-connected memory | Greater expandable capacity than HBM | Farther from accelerators and lower bandwidth | Cache expansion, model tiering, and memory pools |\n| High-bandwidth flash | HBF concept | High NAND-based density and non-volatility | Read latency, write endurance, and control complexity | Less frequently used weights and KV cache tiers |\n| Storage | NVMe SSD | High capacity and low cost per bit | Longer latency than memory | Checkpoints, datasets, and cold data |\n\nThe key is not for either HBM or HBF to win, but to deploy multiple tiers according to how frequently data is used.\n\n## The Next-Generation Memory Competition Revealed by FMS 2026\n\nFMS, held in Santa Clara, United States, in August 2026, addressed post-HBM AI memory and storage architectures as major agenda items. Discussions centered on taller stacks, high-capacity NAND-based tiers, customized memory, and data center connectivity technologies.\n\nSamsung Electronics’ GHBM and the HBF discussed by SK hynix with Google and SanDisk were introduced as examples illustrating this direction. However, it is difficult to conclude that names such as GHBM, HBF, and THBM are all universal generation names finalized under identical JEDEC specifications. Technologies at the corporate announcement stage, joint development concepts, and standardized commercial products must be distinguished from one another.\n\nMoreover, a higher generation name does not necessarily make actual AI services faster. Effective bandwidth, memory capacity, latency, power, cooling, package yield, and software support must all be compared together.\n\n## HBM’s Strengths and Capacity Limitations\n\nHBM vertically stacks multiple DRAM dies and connects them using through-silicon vias and a wide interface. Its key advantage is that it can supply large amounts of data in parallel close to the accelerator, unlike conventional board-level memory.\n\nHowever, HBM capacity cannot be increased indefinitely.\n\n1. As the number of stacked layers increases, manufacturing yield and testing become more difficult.\n2. The package area required to place the GPU and HBM together increases.\n3. Heat generated by the accelerator and memory must be removed from a confined space.\n4. Power delivery networks and interposer wiring also become more complex.\n5. Using expensive HBM to store even infrequently accessed data reduces economic efficiency.\n\nFor this reason, tiering is becoming important, with HBM handling the most frequently used data and the rest being moved to CXL memory, flash, or SSDs.\n\n## Can HBF Replace HBM?\n\nHBF stands for High Bandwidth Flash and is a concept that parallelizes and stacks NAND flash to create a high-bandwidth memory tier closer to accelerators than conventional SSDs. Because NAND offers higher density and non-volatility than DRAM, it has the potential to store more data in the same physical space.\n\nHowever, NAND has different characteristics from DRAM.\n\n- It has longer read latency.\n- Data must be erased before it can be overwritten.\n- Endurance must be managed according to the number of writes.\n- Bad blocks, error correction, and wear leveling must be handled.\n- It is better suited to large sequential accesses than small, irregular accesses.\n\nTherefore, even if HBF is commercialized, it is more likely to function as a **high-capacity tier between HBM and SSDs** than to directly replace HBM. Read-heavy model weights, infrequently reused caches, checkpoints, and retrieval data could be candidates. Its actual suitability will depend on interface standards, latency, endurance, controllers, and inference software support.\n\n## The 3D Packaging Challenges Raised by GHBM and THBM\n\nPlacing accelerators and HBM side by side within a package imposes limits on connection width and package area. To overcome these limitations, concepts have emerged that vertically stack logic and memory to shorten wiring distances.\n\n### A Structure That Places Memory Above the GPU\n\nThe concept introduced as GHBM or Z-axis HBM aims to reduce data movement distances by vertically integrating the GPU and HBM. Numerous short vertical connections are expected to provide high bandwidth and low I/O power.\n\nThe problem is heat. When memory is placed above the GPU, heat generated by the GPU may pass through the memory on its way to the cooling device. The expression “the memory melts” is closer to a metaphor emphasizing the thermal problem than a technical explanation. The actual risks are exceeding the allowable temperatures of the bonding interfaces and memory, increased leakage current, performance throttling, and reduced lifespan.\n\n### Memory Below, GPU Above\n\nTHBM, reportedly proposed by Professor Kim Jung-ho’s team at KAIST, is based on the idea of placing the GPU above the HBM stack so that the heat-generating logic sits closer to the cooling device. This may be advantageous for heat dissipation, but the following challenges remain.\n\n- Mechanical stability of the heavy logic die and memory stack\n- Power delivery and signal routing\n- Bonding yield for dies manufactured using different processes\n- The ability to replace and test defective dies\n- Package design that includes the cooling plate\n\nThe competitiveness of vertical stacking cannot be determined from a conceptual diagram alone. Measurements of thermal resistance, effective bandwidth, yield, and total cost of ownership are required.\n\n## Are Optical Interconnects a Way to Avoid Dependence on Memory?\n\nUsing memory and storage outside the GPU requires data to travel farther. As electrical signals travel longer distances at higher transmission speeds, they require more power for signal conditioning and retransmission. Optical interconnects are attracting attention as a candidate for improving bandwidth density and transmission power in high-speed connections among servers, racks, and clusters.\n\nIt is difficult to explain NVIDIA’s move to strengthen optical networking solely as a strategy to avoid dependence on a particular memory company. The more direct reason is that as accelerator deployments scale beyond a single server to racks and entire data centers, networking becomes a bottleneck for the overall AI system.\n\nOptical links also do not replace HBM. HBM is likely to provide short latency immediately next to accelerators, while optical links connect more distant memory pools and multiple accelerators.\n\n## How Customized HBM Is Changing the Memory Industry\n\nConventional commodity DRAM has largely involved supplying products with the same specifications to multiple customers. HBM requires coordinated design of the GPU package, interposer, base die, power, and thermals, increasing the degree of joint design between customers and memory companies.\n\nCustomized HBM, or CHBM, can incorporate the following functions into the base die.\n\n- Memory control and interface optimization\n- Error correction and reliability management\n- Data compression and movement control\n- Security or virtualization functions\n- Limited data preprocessing and computation\n\nThis structure could elevate memory suppliers from simple component manufacturers to system co-designers. Because volume and specifications are discussed early in development, it may also increase the effects of long-term contracts and customer lock-in.\n\nHowever, customization does not completely eliminate the memory cycle. The pace of AI investment, customer concentration, packaging capacity, yield, and commodity DRAM prices can still cause fluctuations in performance. Products optimized for a particular customer also carry the risk of being difficult to sell to other customers if demand changes.\n\n## Is It Accurate to Say That GPU Development Has Stopped?\n\nIt is difficult to conclude that GPU development has effectively stopped. Accelerators continue to advance through low-precision computation formats, sparsity processing, transformer-specific engines, chiplets, networking, and cooling.\n\nWhat has changed is the evaluation criteria. The following metrics have become more important than the peak computing performance of a single chip.\n\n- Effective memory bandwidth achieved with actual models\n- Time to first token and token generation speed per user\n- Tokens processed per watt\n- Memory capacity and network bandwidth per rack\n- Total cost of serving a model\n\nThe spread of open-source models has not equalized all model capabilities. However, as multiple providers can now use similar models, it is true that hardware operating efficiency and service deployment capabilities have become more important.\n\n## Easily Overlooked Variables: Reliability, Security, and Programming Models\n\nDiscussions of next-generation memory focus on bandwidth and capacity, but other factors determine actual commercialization.\n\n### Data Accuracy and Lifespan\n\nAs memory stacking and density increase, heat, error rates, and lifespan become more important. In AI inference, silent data corruption may manifest as incorrect output rather than an immediate system failure. Error correction, data integrity checks, and fault isolation are as important as performance.\n\n### Security of Shared Memory\n\nWhen multiple accelerators and customers share CXL memory pools or external caches, data isolation, encryption, access control, and residual data deletion are required. As memory capacity grows, the amount of model weights and user context that must be protected also increases.\n\n### Can Developers Use It?\n\nEven if a new memory tier exists, its usefulness will be limited if compilers and inference engines cannot automatically determine data placement. A runtime is needed to manage which tensors and KV caches reside in HBM, HBF, CXL memory, or SSDs. Ultimately, hardware competition leads to competition in memory schedulers and system software.\n\n## Are AI Data Centers Memory Factories?\n\nCalling a large-scale AI data center a “memory factory” is a useful metaphor for emphasizing the strategic importance of memory. Model weights, KV caches, training data, checkpoints, and search indexes are stored across multiple tiers.\n\nHowever, there is insufficient evidence for generalizations claiming that a fixed percentage of data center costs is always spent on memory and power. Cost structures vary depending on the balance between training and inference, electricity prices, server depreciation, networking, cooling, utilization, and model efficiency.\n\nA more accurate conclusion is as follows.\n\n\u003e Future AI data centers will go beyond being places that install large numbers of GPUs and become systems that place data in the most appropriate memory tier and move it using the least possible power.\n\n## Implications for the Korean Semiconductor Industry\n\nKorea has large-scale manufacturing capabilities in HBM and NAND flash, placing it in an important position in the shift toward memory-centric computing. However, memory production volume alone is unlikely to guarantee a long-term advantage.\n\nThe necessary strategies are as follows.\n\n1. Secure the capability to jointly design HBM, HBF, and advanced packaging.\n2. Increase the share of design capabilities in base dies, interface IP, and memory controllers.\n3. Foster companies specializing in thermal management, power semiconductors, optical interconnects, and data center systems.\n4. Build a software ecosystem that enables compilers and inference engines to use Korean-made memory efficiently.\n5. Secure real-world use cases that connect hardware, AI models, and services in smartphones, automobiles, robots, and home appliances.\n6. Manage the risks of dependence on specific customers or a single packaging supply chain.\n\nA position in which “it is difficult to build AI without going through Korea” cannot be created by production volume alone. A difficult-to-replace industrial position emerges when standards, design assets, manufacturing, packaging, software, and end services are connected.\n\n## Outlook: Tiering and Co-Design, Not Replacement\n\nRather than viewing AI semiconductors as being completely replaced from a GPU-centric model by a memory-centric one, it is more accurate to see this as a process in which the boundary between processors and memory becomes blurred.\n\n- HBM handles data that must be accessed most quickly.\n- HBF and CXL memory provide greater capacity.\n- SSDs handle long-term storage and cold data.\n- Optical interconnects reduce the cost of connecting distant resources.\n- Customized base dies and PIM move some computation closer to the data.\n- Inference software determines the tier in which each piece of data should reside.\n\nThe winner in next-generation AI infrastructure is likely to be not the company that creates the single fastest GPU, but the ecosystem that optimizes computing, memory, connectivity, power, cooling, and software as one integrated system.","content_html":"\u003cp\u003eThe competitive criteria for AI semiconductors are expanding beyond simple computation counts to \u003cstrong\u003ehow much data can be stored and moved using little power\u003c/strong\u003e. In large-scale AI inference, GPUs may sit idle not because they cannot perform computations, but because they do not receive the required model weights and KV cache in time.\u003c/p\u003e\n\u003cp\u003eThis change is often described as a “shift from GPU-centric to memory-centric computing.” However, this does not mean that GPUs are disappearing or have stopped advancing. More precisely, it is a move toward jointly designing GPUs, HBM, external memory, storage, networking, and software as a single data movement system.\u003c/p\u003e\n\u003ch2\u003e\n\u003ca href=\"#what-is-memory-centric-computing\" class=\"anchor\" id=\"what-is-memory-centric-computing\"\u003e\u003c/a\u003eWhat Is Memory-Centric Computing?\u003c/h2\u003e\n\u003cp\u003e\u003cstrong\u003eMemory-centric computing is an approach that takes memory location, bandwidth, capacity, and computing capabilities as the starting point of system design to reduce the cost of repeatedly moving data to processors.\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eThe arithmetic throughput of AI chips has increased rapidly, but retrieving data from outside the chip remains relatively slow and consumes significant power. As a result, the following technologies are becoming important together.\u003c/p\u003e\n\u003cul\u003e\n\u003cli\u003eHBM placed close to a GPU or AI accelerator\u003c/li\u003e\n\u003cli\u003e3D packaging that vertically connects memory and logic\u003c/li\u003e\n\u003cli\u003eCustomized HBM that incorporates control or limited computing functions into the base die\u003c/li\u003e\n\u003cli\u003eMemory expansion and pooling using CXL\u003c/li\u003e\n\u003cli\u003eThe HBF concept, which connects NAND flash through a wide interface\u003c/li\u003e\n\u003cli\u003eOptical interconnects intended to reduce transmission power between chips and servers\u003c/li\u003e\n\u003cli\u003ePIM and near-memory computing, which process data close to memory\u003c/li\u003e\n\u003c/ul\u003e\n\u003cp\u003eIn other words, memory-centric computing does not refer to a single memory product. It is a system principle that combines multiple tiers, from fast memory to high-capacity storage, to minimize data movement.\u003c/p\u003e\n\u003ch2\u003e\n\u003ca href=\"#why-ai-inference-intensifies-the-memory-bottleneck\" class=\"anchor\" id=\"why-ai-inference-intensifies-the-memory-bottleneck\"\u003e\u003c/a\u003eWhy AI Inference Intensifies the Memory Bottleneck\u003c/h2\u003e\n\u003ch3\u003e\n\u003ca href=\"#model-weights-and-the-kv-cache-create-different-burdens\" class=\"anchor\" id=\"model-weights-and-the-kv-cache-create-different-burdens\"\u003e\u003c/a\u003eModel Weights and the KV Cache Create Different Burdens\u003c/h3\u003e\n\u003cp\u003eThe memory required for AI inference can broadly be divided into model weights, activations generated during execution, and the KV cache. Model weights occupy a fixed amount of space even when there are no requests, while the KV cache grows according to input length, output length, and the number of concurrent requests.\u003c/p\u003e\n\u003cp\u003eTo avoid recomputing previous tokens from scratch each time, transformer models store attention key and value information for each layer in the KV cache. In simplified terms, the KV cache size for a single request is proportional to the following factors.\u003c/p\u003e\n\u003cp\u003eThe exact KV cache size must be verified from the model architecture and implementation specifications.\u003c/p\u003e\n\u003cp\u003eThe KV cache stores keys and values separately. Therefore, as context grows longer or more users are processed simultaneously, the KV cache grows rapidly. Not every model uses millions of tokens, nor does cache size uniformly increase by hundreds of times, but it is clear that long-context inference and agentic tasks increase memory pressure.\u003c/p\u003e\n\u003ch3\u003e\n\u003ca href=\"#hallucinations-and-memory-capacity-are-not-the-same-problem\" class=\"anchor\" id=\"hallucinations-and-memory-capacity-are-not-the-same-problem\"\u003e\u003c/a\u003eHallucinations and Memory Capacity Are Not the Same Problem\u003c/h3\u003e\n\u003cp\u003eLonger context and retrieval-augmented generation can provide models with more supporting evidence. However, increasing memory alone does not eliminate hallucinations. The quality of search results, prompt design, the model’s reasoning capabilities, source verification, and evaluation frameworks are also necessary.\u003c/p\u003e\n\u003ch3\u003e\n\u003ca href=\"#software-can-reduce-physical-memory-demand\" class=\"anchor\" id=\"software-can-reduce-physical-memory-demand\"\u003e\u003c/a\u003eSoftware Can Reduce Physical Memory Demand\u003c/h3\u003e\n\u003cp\u003eThe KV cache bottleneck is not solved solely by adding hardware.\u003c/p\u003e\n\u003cul\u003e\n\u003cli\u003eMQA and GQA reduce the number of KV heads that must be stored.\u003c/li\u003e\n\u003cli\u003eQuantization reduces the number of bytes used by weights and caches.\u003c/li\u003e\n\u003cli\u003ePagedAttention manages caches in pages, mitigating fragmentation and waste.\u003c/li\u003e\n\u003cli\u003eContinuous batching efficiently groups multiple requests.\u003c/li\u003e\n\u003cli\u003ePrefix caching reuses repeated system prompts or shared context.\u003c/li\u003e\n\u003cli\u003eCache eviction and tiered offloading move less important information to slower memory.\u003c/li\u003e\n\u003c/ul\u003e\n\u003cp\u003eTherefore, the actual amount of memory investment in a data center depends not only on model size but also on the efficiency of the inference engine.\u003c/p\u003e\n\u003ch2\u003e\n\u003ca href=\"#the-memory-hierarchy-of-ai-data-centers\" class=\"anchor\" id=\"the-memory-hierarchy-of-ai-data-centers\"\u003e\u003c/a\u003eThe Memory Hierarchy of AI Data Centers\u003c/h2\u003e\n\u003cp\u003eIt is difficult for a single type of memory to satisfy speed, capacity, cost, and power efficiency requirements all at once. AI data centers are likely to evolve into the following hierarchy.\u003c/p\u003e\n\u003cdiv class=\"overflow-x-auto\"\u003e\u003ctable\u003e\n\u003cthead\u003e\n\u003ctr\u003e\n\u003cth\u003eTier\u003c/th\u003e\n\u003cth\u003eRepresentative Technologies\u003c/th\u003e\n\u003cth\u003eStrengths\u003c/th\u003e\n\u003cth\u003eMain Limitations\u003c/th\u003e\n\u003cth\u003eExpected Role\u003c/th\u003e\n\u003c/tr\u003e\n\u003c/thead\u003e\n\u003ctbody\u003e\n\u003ctr\u003e\n\u003ctd data-label=\"Tier\"\u003eOn-chip\u003c/td\u003e\n\u003ctd data-label=\"Representative Technologies\"\u003eSRAM, registers\u003c/td\u003e\n\u003ctd data-label=\"Strengths\"\u003eShortest latency\u003c/td\u003e\n\u003ctd data-label=\"Main Limitations\"\u003eVery limited capacity and high area cost\u003c/td\u003e\n\u003ctd data-label=\"Expected Role\"\u003eImmediately needed data and intermediate computation results\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd data-label=\"Tier\"\u003eAdjacent to accelerator\u003c/td\u003e\n\u003ctd data-label=\"Representative Technologies\"\u003eHBM\u003c/td\u003e\n\u003ctd data-label=\"Strengths\"\u003eHigh bandwidth and relatively short latency\u003c/td\u003e\n\u003ctd data-label=\"Main Limitations\"\u003eCapacity, packaging cost, and thermal constraints\u003c/td\u003e\n\u003ctd data-label=\"Expected Role\"\u003eActive weights and frequently used KV cache\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd data-label=\"Tier\"\u003eServer memory\u003c/td\u003e\n\u003ctd data-label=\"Representative Technologies\"\u003eDDR, CXL-connected memory\u003c/td\u003e\n\u003ctd data-label=\"Strengths\"\u003eGreater expandable capacity than HBM\u003c/td\u003e\n\u003ctd data-label=\"Main Limitations\"\u003eFarther from accelerators and lower bandwidth\u003c/td\u003e\n\u003ctd data-label=\"Expected Role\"\u003eCache expansion, model tiering, and memory pools\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd data-label=\"Tier\"\u003eHigh-bandwidth flash\u003c/td\u003e\n\u003ctd data-label=\"Representative Technologies\"\u003eHBF concept\u003c/td\u003e\n\u003ctd data-label=\"Strengths\"\u003eHigh NAND-based density and non-volatility\u003c/td\u003e\n\u003ctd data-label=\"Main Limitations\"\u003eRead latency, write endurance, and control complexity\u003c/td\u003e\n\u003ctd data-label=\"Expected Role\"\u003eLess frequently used weights and KV cache tiers\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd data-label=\"Tier\"\u003eStorage\u003c/td\u003e\n\u003ctd data-label=\"Representative Technologies\"\u003eNVMe SSD\u003c/td\u003e\n\u003ctd data-label=\"Strengths\"\u003eHigh capacity and low cost per bit\u003c/td\u003e\n\u003ctd data-label=\"Main Limitations\"\u003eLonger latency than memory\u003c/td\u003e\n\u003ctd data-label=\"Expected Role\"\u003eCheckpoints, datasets, and cold data\u003c/td\u003e\n\u003c/tr\u003e\n\u003c/tbody\u003e\n\u003c/table\u003e\u003c/div\u003e\n\u003cp\u003eThe key is not for either HBM or HBF to win, but to deploy multiple tiers according to how frequently data is used.\u003c/p\u003e\n\u003ch2\u003e\n\u003ca href=\"#the-next-generation-memory-competition-revealed-by-fms-2026\" class=\"anchor\" id=\"the-next-generation-memory-competition-revealed-by-fms-2026\"\u003e\u003c/a\u003eThe Next-Generation Memory Competition Revealed by FMS 2026\u003c/h2\u003e\n\u003cp\u003eFMS, held in Santa Clara, United States, in August 2026, addressed post-HBM AI memory and storage architectures as major agenda items. Discussions centered on taller stacks, high-capacity NAND-based tiers, customized memory, and data center connectivity technologies.\u003c/p\u003e\n\u003cp\u003eSamsung Electronics’ GHBM and the HBF discussed by SK hynix with Google and SanDisk were introduced as examples illustrating this direction. However, it is difficult to conclude that names such as GHBM, HBF, and THBM are all universal generation names finalized under identical JEDEC specifications. Technologies at the corporate announcement stage, joint development concepts, and standardized commercial products must be distinguished from one another.\u003c/p\u003e\n\u003cp\u003eMoreover, a higher generation name does not necessarily make actual AI services faster. Effective bandwidth, memory capacity, latency, power, cooling, package yield, and software support must all be compared together.\u003c/p\u003e\n\u003ch2\u003e\n\u003ca href=\"#hbms-strengths-and-capacity-limitations\" class=\"anchor\" id=\"hbms-strengths-and-capacity-limitations\"\u003e\u003c/a\u003eHBM’s Strengths and Capacity Limitations\u003c/h2\u003e\n\u003cp\u003eHBM vertically stacks multiple DRAM dies and connects them using through-silicon vias and a wide interface. Its key advantage is that it can supply large amounts of data in parallel close to the accelerator, unlike conventional board-level memory.\u003c/p\u003e\n\u003cp\u003eHowever, HBM capacity cannot be increased indefinitely.\u003c/p\u003e\n\u003col\u003e\n\u003cli\u003eAs the number of stacked layers increases, manufacturing yield and testing become more difficult.\u003c/li\u003e\n\u003cli\u003eThe package area required to place the GPU and HBM together increases.\u003c/li\u003e\n\u003cli\u003eHeat generated by the accelerator and memory must be removed from a confined space.\u003c/li\u003e\n\u003cli\u003ePower delivery networks and interposer wiring also become more complex.\u003c/li\u003e\n\u003cli\u003eUsing expensive HBM to store even infrequently accessed data reduces economic efficiency.\u003c/li\u003e\n\u003c/ol\u003e\n\u003cp\u003eFor this reason, tiering is becoming important, with HBM handling the most frequently used data and the rest being moved to CXL memory, flash, or SSDs.\u003c/p\u003e\n\u003ch2\u003e\n\u003ca href=\"#can-hbf-replace-hbm\" class=\"anchor\" id=\"can-hbf-replace-hbm\"\u003e\u003c/a\u003eCan HBF Replace HBM?\u003c/h2\u003e\n\u003cp\u003eHBF stands for High Bandwidth Flash and is a concept that parallelizes and stacks NAND flash to create a high-bandwidth memory tier closer to accelerators than conventional SSDs. Because NAND offers higher density and non-volatility than DRAM, it has the potential to store more data in the same physical space.\u003c/p\u003e\n\u003cp\u003eHowever, NAND has different characteristics from DRAM.\u003c/p\u003e\n\u003cul\u003e\n\u003cli\u003eIt has longer read latency.\u003c/li\u003e\n\u003cli\u003eData must be erased before it can be overwritten.\u003c/li\u003e\n\u003cli\u003eEndurance must be managed according to the number of writes.\u003c/li\u003e\n\u003cli\u003eBad blocks, error correction, and wear leveling must be handled.\u003c/li\u003e\n\u003cli\u003eIt is better suited to large sequential accesses than small, irregular accesses.\u003c/li\u003e\n\u003c/ul\u003e\n\u003cp\u003eTherefore, even if HBF is commercialized, it is more likely to function as a \u003cstrong\u003ehigh-capacity tier between HBM and SSDs\u003c/strong\u003e than to directly replace HBM. Read-heavy model weights, infrequently reused caches, checkpoints, and retrieval data could be candidates. Its actual suitability will depend on interface standards, latency, endurance, controllers, and inference software support.\u003c/p\u003e\n\u003ch2\u003e\n\u003ca href=\"#the-3d-packaging-challenges-raised-by-ghbm-and-thbm\" class=\"anchor\" id=\"the-3d-packaging-challenges-raised-by-ghbm-and-thbm\"\u003e\u003c/a\u003eThe 3D Packaging Challenges Raised by GHBM and THBM\u003c/h2\u003e\n\u003cp\u003ePlacing accelerators and HBM side by side within a package imposes limits on connection width and package area. To overcome these limitations, concepts have emerged that vertically stack logic and memory to shorten wiring distances.\u003c/p\u003e\n\u003ch3\u003e\n\u003ca href=\"#a-structure-that-places-memory-above-the-gpu\" class=\"anchor\" id=\"a-structure-that-places-memory-above-the-gpu\"\u003e\u003c/a\u003eA Structure That Places Memory Above the GPU\u003c/h3\u003e\n\u003cp\u003eThe concept introduced as GHBM or Z-axis HBM aims to reduce data movement distances by vertically integrating the GPU and HBM. Numerous short vertical connections are expected to provide high bandwidth and low I/O power.\u003c/p\u003e\n\u003cp\u003eThe problem is heat. When memory is placed above the GPU, heat generated by the GPU may pass through the memory on its way to the cooling device. The expression “the memory melts” is closer to a metaphor emphasizing the thermal problem than a technical explanation. The actual risks are exceeding the allowable temperatures of the bonding interfaces and memory, increased leakage current, performance throttling, and reduced lifespan.\u003c/p\u003e\n\u003ch3\u003e\n\u003ca href=\"#memory-below-gpu-above\" class=\"anchor\" id=\"memory-below-gpu-above\"\u003e\u003c/a\u003eMemory Below, GPU Above\u003c/h3\u003e\n\u003cp\u003eTHBM, reportedly proposed by Professor Kim Jung-ho’s team at KAIST, is based on the idea of placing the GPU above the HBM stack so that the heat-generating logic sits closer to the cooling device. This may be advantageous for heat dissipation, but the following challenges remain.\u003c/p\u003e\n\u003cul\u003e\n\u003cli\u003eMechanical stability of the heavy logic die and memory stack\u003c/li\u003e\n\u003cli\u003ePower delivery and signal routing\u003c/li\u003e\n\u003cli\u003eBonding yield for dies manufactured using different processes\u003c/li\u003e\n\u003cli\u003eThe ability to replace and test defective dies\u003c/li\u003e\n\u003cli\u003ePackage design that includes the cooling plate\u003c/li\u003e\n\u003c/ul\u003e\n\u003cp\u003eThe competitiveness of vertical stacking cannot be determined from a conceptual diagram alone. Measurements of thermal resistance, effective bandwidth, yield, and total cost of ownership are required.\u003c/p\u003e\n\u003ch2\u003e\n\u003ca href=\"#are-optical-interconnects-a-way-to-avoid-dependence-on-memory\" class=\"anchor\" id=\"are-optical-interconnects-a-way-to-avoid-dependence-on-memory\"\u003e\u003c/a\u003eAre Optical Interconnects a Way to Avoid Dependence on Memory?\u003c/h2\u003e\n\u003cp\u003eUsing memory and storage outside the GPU requires data to travel farther. As electrical signals travel longer distances at higher transmission speeds, they require more power for signal conditioning and retransmission. Optical interconnects are attracting attention as a candidate for improving bandwidth density and transmission power in high-speed connections among servers, racks, and clusters.\u003c/p\u003e\n\u003cp\u003eIt is difficult to explain NVIDIA’s move to strengthen optical networking solely as a strategy to avoid dependence on a particular memory company. The more direct reason is that as accelerator deployments scale beyond a single server to racks and entire data centers, networking becomes a bottleneck for the overall AI system.\u003c/p\u003e\n\u003cp\u003eOptical links also do not replace HBM. HBM is likely to provide short latency immediately next to accelerators, while optical links connect more distant memory pools and multiple accelerators.\u003c/p\u003e\n\u003ch2\u003e\n\u003ca href=\"#how-customized-hbm-is-changing-the-memory-industry\" class=\"anchor\" id=\"how-customized-hbm-is-changing-the-memory-industry\"\u003e\u003c/a\u003eHow Customized HBM Is Changing the Memory Industry\u003c/h2\u003e\n\u003cp\u003eConventional commodity DRAM has largely involved supplying products with the same specifications to multiple customers. HBM requires coordinated design of the GPU package, interposer, base die, power, and thermals, increasing the degree of joint design between customers and memory companies.\u003c/p\u003e\n\u003cp\u003eCustomized HBM, or CHBM, can incorporate the following functions into the base die.\u003c/p\u003e\n\u003cul\u003e\n\u003cli\u003eMemory control and interface optimization\u003c/li\u003e\n\u003cli\u003eError correction and reliability management\u003c/li\u003e\n\u003cli\u003eData compression and movement control\u003c/li\u003e\n\u003cli\u003eSecurity or virtualization functions\u003c/li\u003e\n\u003cli\u003eLimited data preprocessing and computation\u003c/li\u003e\n\u003c/ul\u003e\n\u003cp\u003eThis structure could elevate memory suppliers from simple component manufacturers to system co-designers. Because volume and specifications are discussed early in development, it may also increase the effects of long-term contracts and customer lock-in.\u003c/p\u003e\n\u003cp\u003eHowever, customization does not completely eliminate the memory cycle. The pace of AI investment, customer concentration, packaging capacity, yield, and commodity DRAM prices can still cause fluctuations in performance. Products optimized for a particular customer also carry the risk of being difficult to sell to other customers if demand changes.\u003c/p\u003e\n\u003ch2\u003e\n\u003ca href=\"#is-it-accurate-to-say-that-gpu-development-has-stopped\" class=\"anchor\" id=\"is-it-accurate-to-say-that-gpu-development-has-stopped\"\u003e\u003c/a\u003eIs It Accurate to Say That GPU Development Has Stopped?\u003c/h2\u003e\n\u003cp\u003eIt is difficult to conclude that GPU development has effectively stopped. Accelerators continue to advance through low-precision computation formats, sparsity processing, transformer-specific engines, chiplets, networking, and cooling.\u003c/p\u003e\n\u003cp\u003eWhat has changed is the evaluation criteria. The following metrics have become more important than the peak computing performance of a single chip.\u003c/p\u003e\n\u003cul\u003e\n\u003cli\u003eEffective memory bandwidth achieved with actual models\u003c/li\u003e\n\u003cli\u003eTime to first token and token generation speed per user\u003c/li\u003e\n\u003cli\u003eTokens processed per watt\u003c/li\u003e\n\u003cli\u003eMemory capacity and network bandwidth per rack\u003c/li\u003e\n\u003cli\u003eTotal cost of serving a model\u003c/li\u003e\n\u003c/ul\u003e\n\u003cp\u003eThe spread of open-source models has not equalized all model capabilities. However, as multiple providers can now use similar models, it is true that hardware operating efficiency and service deployment capabilities have become more important.\u003c/p\u003e\n\u003ch2\u003e\n\u003ca href=\"#easily-overlooked-variables-reliability-security-and-programming-models\" class=\"anchor\" id=\"easily-overlooked-variables-reliability-security-and-programming-models\"\u003e\u003c/a\u003eEasily Overlooked Variables: Reliability, Security, and Programming Models\u003c/h2\u003e\n\u003cp\u003eDiscussions of next-generation memory focus on bandwidth and capacity, but other factors determine actual commercialization.\u003c/p\u003e\n\u003ch3\u003e\n\u003ca href=\"#data-accuracy-and-lifespan\" class=\"anchor\" id=\"data-accuracy-and-lifespan\"\u003e\u003c/a\u003eData Accuracy and Lifespan\u003c/h3\u003e\n\u003cp\u003eAs memory stacking and density increase, heat, error rates, and lifespan become more important. In AI inference, silent data corruption may manifest as incorrect output rather than an immediate system failure. Error correction, data integrity checks, and fault isolation are as important as performance.\u003c/p\u003e\n\u003ch3\u003e\n\u003ca href=\"#security-of-shared-memory\" class=\"anchor\" id=\"security-of-shared-memory\"\u003e\u003c/a\u003eSecurity of Shared Memory\u003c/h3\u003e\n\u003cp\u003eWhen multiple accelerators and customers share CXL memory pools or external caches, data isolation, encryption, access control, and residual data deletion are required. As memory capacity grows, the amount of model weights and user context that must be protected also increases.\u003c/p\u003e\n\u003ch3\u003e\n\u003ca href=\"#can-developers-use-it\" class=\"anchor\" id=\"can-developers-use-it\"\u003e\u003c/a\u003eCan Developers Use It?\u003c/h3\u003e\n\u003cp\u003eEven if a new memory tier exists, its usefulness will be limited if compilers and inference engines cannot automatically determine data placement. A runtime is needed to manage which tensors and KV caches reside in HBM, HBF, CXL memory, or SSDs. Ultimately, hardware competition leads to competition in memory schedulers and system software.\u003c/p\u003e\n\u003ch2\u003e\n\u003ca href=\"#are-ai-data-centers-memory-factories\" class=\"anchor\" id=\"are-ai-data-centers-memory-factories\"\u003e\u003c/a\u003eAre AI Data Centers Memory Factories?\u003c/h2\u003e\n\u003cp\u003eCalling a large-scale AI data center a “memory factory” is a useful metaphor for emphasizing the strategic importance of memory. Model weights, KV caches, training data, checkpoints, and search indexes are stored across multiple tiers.\u003c/p\u003e\n\u003cp\u003eHowever, there is insufficient evidence for generalizations claiming that a fixed percentage of data center costs is always spent on memory and power. Cost structures vary depending on the balance between training and inference, electricity prices, server depreciation, networking, cooling, utilization, and model efficiency.\u003c/p\u003e\n\u003cp\u003eA more accurate conclusion is as follows.\u003c/p\u003e\n\u003cblockquote\u003e\n\u003cp\u003eFuture AI data centers will go beyond being places that install large numbers of GPUs and become systems that place data in the most appropriate memory tier and move it using the least possible power.\u003c/p\u003e\n\u003c/blockquote\u003e\n\u003ch2\u003e\n\u003ca href=\"#implications-for-the-korean-semiconductor-industry\" class=\"anchor\" id=\"implications-for-the-korean-semiconductor-industry\"\u003e\u003c/a\u003eImplications for the Korean Semiconductor Industry\u003c/h2\u003e\n\u003cp\u003eKorea has large-scale manufacturing capabilities in HBM and NAND flash, placing it in an important position in the shift toward memory-centric computing. However, memory production volume alone is unlikely to guarantee a long-term advantage.\u003c/p\u003e\n\u003cp\u003eThe necessary strategies are as follows.\u003c/p\u003e\n\u003col\u003e\n\u003cli\u003eSecure the capability to jointly design HBM, HBF, and advanced packaging.\u003c/li\u003e\n\u003cli\u003eIncrease the share of design capabilities in base dies, interface IP, and memory controllers.\u003c/li\u003e\n\u003cli\u003eFoster companies specializing in thermal management, power semiconductors, optical interconnects, and data center systems.\u003c/li\u003e\n\u003cli\u003eBuild a software ecosystem that enables compilers and inference engines to use Korean-made memory efficiently.\u003c/li\u003e\n\u003cli\u003eSecure real-world use cases that connect hardware, AI models, and services in smartphones, automobiles, robots, and home appliances.\u003c/li\u003e\n\u003cli\u003eManage the risks of dependence on specific customers or a single packaging supply chain.\u003c/li\u003e\n\u003c/ol\u003e\n\u003cp\u003eA position in which “it is difficult to build AI without going through Korea” cannot be created by production volume alone. A difficult-to-replace industrial position emerges when standards, design assets, manufacturing, packaging, software, and end services are connected.\u003c/p\u003e\n\u003ch2\u003e\n\u003ca href=\"#outlook-tiering-and-co-design-not-replacement\" class=\"anchor\" id=\"outlook-tiering-and-co-design-not-replacement\"\u003e\u003c/a\u003eOutlook: Tiering and Co-Design, Not Replacement\u003c/h2\u003e\n\u003cp\u003eRather than viewing AI semiconductors as being completely replaced from a GPU-centric model by a memory-centric one, it is more accurate to see this as a process in which the boundary between processors and memory becomes blurred.\u003c/p\u003e\n\u003cul\u003e\n\u003cli\u003eHBM handles data that must be accessed most quickly.\u003c/li\u003e\n\u003cli\u003eHBF and CXL memory provide greater capacity.\u003c/li\u003e\n\u003cli\u003eSSDs handle long-term storage and cold data.\u003c/li\u003e\n\u003cli\u003eOptical interconnects reduce the cost of connecting distant resources.\u003c/li\u003e\n\u003cli\u003eCustomized base dies and PIM move some computation closer to the data.\u003c/li\u003e\n\u003cli\u003eInference software determines the tier in which each piece of data should reside.\u003c/li\u003e\n\u003c/ul\u003e\n\u003cp\u003eThe winner in next-generation AI infrastructure is likely to be not the company that creates the single fastest GPU, but the ecosystem that optimizes computing, memory, connectivity, power, cooling, and software as one integrated system.\u003c/p\u003e\n","tags":["Semiconductors","AI Data Center","SK hynix","AI chips","HBM"],"faqs":[{"question":"Does memory-centric computing mean replacing GPUs with memory?","answer":"No. GPUs and other accelerators continue to handle computation. Memory-centric computing is an approach that jointly designs accelerators, HBM, external memory, storage, and networks to reduce the time and power required for data movement."},{"question":"Why does the KV cache grow with long contexts?","answer":"Transformers store the key and value information of previous tokens for each layer to avoid repeating the same computation. The amount of storage is generally proportional to the number of tokens, the number of layers, the number of KV heads, and the size of the data format, so long contexts and many concurrent requests increase memory usage."},{"question":"Is HBF always better than HBM if it has greater capacity?","answer":"No. NAND-based HBF offers the advantages of high density and non-volatility, but it has higher latency than DRAM-based HBM, and write endurance and error management are more complex. A tiered configuration that places frequently used data in HBM and less frequently used data in HBF is more practical."},{"question":"What is the difference between HBF and a conventional NVMe SSD?","answer":"HBF is a concept intended to provide higher bandwidth than conventional SSDs by connecting NAND flash closer to the accelerator through a wider, more parallel interface. Specific performance and connection methods may vary depending on the product and the outcome of standardization."},{"question":"What are the advantages of vertically stacking a GPU and HBM?","answer":"Shorter connection distances and the ability to use many vertical interconnects can offer advantages in bandwidth and I/O power. On the other hand, thermal density, power delivery, bonding yield, testing, and cooling become more challenging."},{"question":"Can optical interconnects replace HBM?","answer":"Optical interconnects are well suited to connecting multiple accelerators or memory resources over long distances, but they do not directly replace the low latency of HBM located right next to an accelerator. The two technologies are likely to serve different distances and memory tiers."},{"question":"Can custom HBM eliminate memory price cycles?","answer":"Custom designs and long-term supply contracts can improve price stability and strengthen customer relationships compared with commodity memory. However, they do not eliminate the effects of fluctuations in AI investment, production capacity, yield, customer concentration, or commodity DRAM prices."},{"question":"Does supporting long contexts eliminate AI hallucinations?","answer":"No. Long contexts can provide more supporting evidence, but poor-quality retrieved material, limited model capabilities, poorly constructed instructions, and inadequate source verification can still lead to incorrect answers. Expanding memory is only one way to mitigate hallucinations."},{"question":"Are GHBM, HBF, and THBM already finalized industry standards?","answer":"Not all of these terms should be regarded as finalized standards at the same level. Some may be names used in corporate announcements or research proposals, so the specifications of standards bodies such as JEDEC, manufacturers' final specifications, and whether they have actually entered mass production must be verified separately."}],"sources":[{"url":"https://futurememorystorage.com/","title":"FMS: the Future of Memory and Storage","type":"source"},{"url":"https://arxiv.org/abs/2309.06180","title":"Efficient Memory Management for Large Language Model Serving with PagedAttention","type":"source"},{"url":"https://arxiv.org/abs/2205.14135","title":"FlashAttention: Fast and Memory-Efficient Exact Attention with IO-Awareness","type":"source"},{"url":"https://developer.nvidia.com/blog/mastering-llm-techniques-inference-optimization/","title":"Mastering LLM Techniques: Inference Optimization","type":"source"},{"url":"https://www.cxlconsortium.org/","title":"Compute Express Link Consortium","type":"source"},{"url":"https://www.uciexpress.org/","title":"UCIe Consortium","type":"source"}],"images":[{"id":716,"url":"https://injoys.com/rails/active_storage/blobs/proxy/eyJfcmFpbHMiOnsiZGF0YSI6OTAxOCwicHVyIjoiYmxvYl9pZCJ9fQ==--5e9ff3355e5af64800fe3a3753eb07a1847f7fba/ai-db43622c.webp","is_representative":true,"generation_method":"ai_image","license":"ai_generated","mime_type":"image/webp","translations":{"ko":{"alt":"중앙 AI 칩과 RAM 모듈, 적층 메모리, 서버, 저장장치가 데이터 경로로 연결된 개념도","caption":"AI 반도체를 중심으로 메모리와 서버, 저장장치 사이의 데이터 흐름을 시각화했다.","description":null},"en":{"alt":"Central AI chip linked by data paths to RAM, stacked memory, servers, and storage","caption":"The illustration visualizes data flowing between an AI chip, memory, servers, and storage.","description":null},"ja":{"alt":"中央のAIチップとRAM、積層メモリ、サーバー、ストレージをデータ経路で結んだ概念図","caption":"AIチップを中心に、メモリやサーバー、ストレージ間のデータの流れを示している。","description":null},"es":{"alt":"Chip de IA central conectado por rutas de datos a RAM, memoria apilada, servidores y almacenamiento","caption":"La ilustración muestra el flujo de datos entre un chip de IA, la memoria, los servidores y el almacenamiento.","description":null},"id":{"alt":"Chip AI pusat terhubung melalui jalur data ke RAM, memori bertumpuk, server, dan penyimpanan","caption":"Ilustrasi ini memvisualisasikan aliran data antara chip AI, memori, server, dan penyimpanan.","description":null},"pt":{"alt":"Chip de IA central ligado por fluxos de dados à RAM, memória empilhada, servidores e armazenamento","caption":"A ilustração mostra o fluxo de dados entre um chip de IA, a memória, os servidores e o armazenamento.","description":null},"zh-hant":{"alt":"中央AI晶片透過資料路徑連接RAM、堆疊記憶體、伺服器與儲存裝置","caption":"插圖呈現AI晶片與記憶體、伺服器及儲存裝置之間的資料流動。","description":null},"de":{"alt":"Zentraler KI-Chip, über Datenpfade mit RAM, Stapelspeicher, Servern und Speichern verbunden","caption":"Die Illustration zeigt den Datenfluss zwischen einem KI-Chip, Speicher, Servern und Datenspeichern.","description":null}}},{"id":717,"url":"https://injoys.com/rails/active_storage/blobs/proxy/eyJfcmFpbHMiOnsiZGF0YSI6OTAyNCwicHVyIjoiYmxvYl9pZCJ9fQ==--0b4dbc6fd04a7a2893bbf9865c8b7e32463f6e20/ai-29d9b4a3.webp","is_representative":false,"generation_method":"ai_image","license":"ai_generated","mime_type":"image/webp","translations":{"ko":{"alt":"적층 메모리와 프로세서, 서버를 고속 링크로 연결한 AI 반도체 구조 일러스트","caption":"적층 메모리와 서버 간 데이터 흐름을 중심으로 AI 반도체 구조를 표현했다.","description":null},"en":{"alt":"Exploded AI chip with stacked memory, processor layers, server racks, and glowing data links","caption":"The illustration highlights data flow between stacked memory, processors, and servers.","description":null},"ja":{"alt":"積層メモリとプロセッサ、サーバーを高速リンクで結ぶAI半導体の構造図","caption":"積層メモリとサーバー間のデータフローを中心にAI半導体の構造を表している。","description":null},"es":{"alt":"Chip de IA por capas con memoria apilada, procesadores, servidores y enlaces de datos luminosos","caption":"La ilustración destaca el flujo de datos entre la memoria apilada, los procesadores y los servidores.","description":null},"id":{"alt":"Chip AI berlapis dengan memori bertumpuk, prosesor, rak server, dan jalur data bercahaya","caption":"Ilustrasi ini menyoroti aliran data antara memori bertumpuk, prosesor, dan server.","description":null},"pt":{"alt":"Chip de IA em camadas com memória empilhada, processadores, servidores e conexões luminosas","caption":"A ilustração destaca o fluxo de dados entre memória empilhada, processadores e servidores.","description":null},"zh-hant":{"alt":"分層AI晶片結合堆疊記憶體、處理器、伺服器機櫃與發光資料連線","caption":"此圖呈現堆疊記憶體、處理器與伺服器之間的資料流動。","description":null},"de":{"alt":"Mehrschichtiger KI-Chip mit gestapeltem Speicher, Prozessoren, Serverracks und leuchtenden Datenleitungen","caption":"Die Illustration zeigt den Datenfluss zwischen gestapeltem Speicher, Prozessoren und Servern.","description":null}}}],"published_at":"2026-08-17T21:47:47+09:00","updated_at":"2026-08-17T21:47:47+09:00","license":"cc_by","translation_status":"reviewed","available_locales":["ko","en","ja","es"],"data_locales":["ko","en","ja","es","id","pt","zh-hant","de"],"url":"https://injoys.com/en/articles/memory-centric-ai-chips-hbm-hbf-packaging"}