{"content_id":"vmz91vr9li","slug":"ai-semiconductor-substrate-glass-transition","locale":"en","schema_type":"TechArticle","category":"trends","category_name":"Trends","title":"AI Chip Substrates: When to Switch to Glass","summary":"AI chip substrates are performance-critical components that carry signals and power between chiplets and HBM. This guide explains the distinct roles and commercialization requirements of FC-BGA, multilayer PCBs, MLCC, and glass substrates.","sponsorship_disclosure":null,"affiliate_disclosure":null,"commerce_disclosure":null,"author":{"name":"Injoys Editorial Team","url":"https://injoys.com/ko/about"},"key_points":["FC-BGA is a package substrate that connects chips to the system board.","Multilayer PCBs connect multiple packages and components at the system level.","Glass substrates offer flatness and dimensional stability, but yield and processability remain challenges.","CPO can be implemented without glass substrates, so the adoption timelines for the two technologies may differ.","Investment decisions should distinguish among development announcements, customer certification, mass production, and revenue."],"content_markdown":"AI semiconductor substrates are performance-critical components that connect chiplets and HBM while distributing power and signals. FC-BGA and high-layer-count PCBs are already in use, but glass substrates still require validation for mass production. Investment decisions should distinguish technical feasibility from actual revenue.\n\nTechnical reference: Intel Newsroom’s announcement on glass substrates; verify the announcement date and subsequent schedules in each company’s latest disclosures\n\n## The Role of Substrates in AI Semiconductors\n\nA substrate provides an electrical interconnection network in addition to serving as a board that secures chips. Signal paths and power networks are also formed within the substrate. Package size and wiring density affect system performance.\n\nAI accelerators do not consist solely of GPUs or dedicated computing chips. HBM and input/output chiplets are also connected over short distances. Heterogeneous integration combines chips made with different processes into a single package.\n\nChiplets are an approach that divides a large monolithic chip into multiple functional blocks. Not all chiplets automatically improve cost or yield. Interface and packaging costs must also be included in the calculation.\n\nSubstrates perform the following functions.\n\n- High-speed signal connections between chips\n- Stable distribution of power and ground\n- Support for heat-transfer paths from chips\n- Connection of terminals with different sizes and pitches\n- Mechanical attachment of the package to the system board\n\n## The Precise Distinction Between FC-BGA and ABF\n\nFC-BGA is a package structure widely used for high-performance chips. The chip is connected face-down to the substrate through bumps. Solder balls beneath the substrate connect it to the system board.\n\nABF does not mean FC-BGA itself. ABF is a family of build-up insulating materials used in fine wiring layers. Therefore, using FC-BGA and ABF substrate as synonyms in every context is inaccurate.\n\nAI packages may require large areas and many input/output connections. Manufacturing becomes more difficult as the number of layers and wiring density increase. However, whether shortages exist varies by period and specification.\n\n## Comparison of High-Layer-Count PCBs and Package Substrates\n\nThe two types of substrates differ in mounting location and wiring precision. FC-BGA is placed directly beneath the semiconductor die. High-layer-count PCBs connect multiple packages and components at the system level.\n\n| Category | FC-BGA Package Substrate | High-Layer-Count PCB·MLB | Glass-Core Substrate·Interposer |\n|---|---|---|---|\n| Primary location | Between the semiconductor die and system board | Main board in servers and networking equipment | Inside the package or in an intermediate interconnection layer |\n| Primary role | Fine-pitch conversion and signal·power connections | System-level connection of packages and connectors | Large-area fine wiring and dimensional stability |\n| Key challenges | Fine wiring, warpage, yield | Interlayer alignment, signal loss, drilling | Breakage, through-glass vias, metal adhesion, yield |\n| Market stage | Commercial mass production | Commercial mass production | Development·trial production·customer qualification coexist |\n| Metrics to verify | Product specifications and utilization rate | Share of revenue from high-layer-count products and customer qualification | Pilot yield and acquisition of mass-production customers |\n\nMLB is a broad term referring to multilayer printed circuit boards. Not every MLB is a high-value-added product for AI servers. It is also difficult to assess product complexity and profitability based solely on the number of layers.\n\nFor high-speed signals, materials and stack-up structures work together. Insertion loss and impedance control must also be examined. Connectors and via structures also affect overall performance.\n\n## The Relationship Between MLCC and Substrates\n\nMLCC is not a substrate but a passive electronic component. It stores electrical charge to mitigate sudden voltage fluctuations. Around processors, it is used for decoupling and noise suppression.\n\nAs AI accelerators consume more power, power-network design becomes more difficult. The required number and specifications of MLCCs vary by product. Demand volume cannot be calculated uniformly based only on improvements in chip performance.\n\nWhen assessing potential benefits for MLCC suppliers, the product mix matters more than unit count. Rated voltage and capacitance affect unit prices. Size and temperature characteristics also determine actual adoption.\n\n## Why Glass Substrates Are Drawing Attention\n\nGlass may offer advantages in flatness and dimensional stability. Its coefficient of thermal expansion can also be adjusted depending on composition and design. These properties are advantageous for reducing alignment errors in large packages.\n\nGlass cores may require through-glass vias. Laser processing and metal-filling processes are used. Microcracks and metal adhesion affect yield.\n\nGlass does not always provide better heat dissipation than plastic. Thermal performance depends on the material’s thermal conductivity and the overall package structure. Actual cooling is evaluated by including heat sinks and cooling systems.\n\nIntel announced glass substrate technology for next-generation advanced packaging, and the announcement date can be verified in Intel Newsroom’s official announcement. This does not mean an immediate industry-wide transition to mass production. Customer qualification and adoption timelines for each company should be verified in the latest disclosures.\n\n## Conditions Linking Glass Substrates and Optical Communications\n\nGlass substrates and CPO may be related, but the relationship is not essential. CPO is a technology that places optical engines close to switch chips. Its purpose is to reduce the distance and power issues of copper interconnections.\n\nThe mere fact that glass is transparent does not reduce optical loss. The material and geometry of the optical waveguide determine signal loss. Coupling structures and wavelength characteristics must also be designed separately.\n\nCPO can also be implemented with silicon photonics and organic substrates. Glass substrates are one potential future integration option. Treating the commercialization schedules of the two technologies as one leads to errors.\n\n## Substrate Selection by Requirement\n\nSubstrate selection varies depending on package size and input/output density. No single material will replace every AI system. Cost and existing production facilities are also adoption criteria.\n\n| Required condition | Technology considered first | Rationale |\n|---|---|---|\n| High-performance processor packaging | FC-BGA | Suitable for fine wiring and input/output connections |\n| System-level connection of multiple packages | High-layer-count PCB | Handles board-level interconnections and power distribution |\n| Ultra-fine connections between chiplets | Silicon interposer or high-density bridge | Enables short, dense wiring |\n| Dimensional stability in large packages | Consider glass-core substrates | Can utilize flatness and thermal expansion properties |\n| Integration of short-range optical input/output | CPO and optical waveguide technology | Can reduce electrical interconnection distances |\n| Suppression of voltage fluctuations | MLCC and power-management circuits | Provide instantaneous current and mitigate noise |\n\n## Example of Signal-Path Calculation\n\nPackage performance can be assessed by dividing it into the entire signal path. For example, multiple interconnection segments exist between a GPU and HBM. Improving only one segment may leave the overall bottleneck unresolved.\n\n1. Check the bump connections between the GPU and HBM.\n2. Check the wiring structure of the interposer or bridge.\n3. Distinguish the signal layers from the power layers in the package substrate.\n4. Check the connections between the solder balls and high-layer-count PCB.\n5. Add up losses through the connectors and network optical modules.\n\nNo common fixed values can be applied to this example. This is because wiring lengths and data rates differ by product. Calculations require the vendor’s design rules and measurement results.\n\n## Common Mistakes and Misconceptions\n\nA frequent mistake is treating technological direction and investment performance as the same thing. Profitability may deteriorate even as technology adoption increases. In the early stages, depreciation and low yields raise costs.\n\n- Treating FC-BGA and ABF as complete synonyms.\n- Interpreting every MLB as being for AI servers.\n- Assuming the number of MLCCs installed is the same in every AI accelerator.\n- Assuming glass always has better heat-dissipation performance than organic materials.\n- Concluding that optical communications will adopt glass based solely on its transparency.\n- Interpreting a development announcement as customer qualification or mass-production revenue.\n- Failing to verify the survey date and scope of market-share figures.\n\nA specific company’s market share may vary by research firm. Classification criteria for AI server applications are also not standardized. Figures without sources and reference years are difficult to use as an investment basis.\n\n## Metrics for Verifying Companies and Industries\n\nCompanies involved in glass substrates should be evaluated by production stage. Research and development and pilot production differ from mass production. Mass-production facilities also do not guarantee customer revenue.\n\n| Verification stage | Facts to verify | Documents to check |\n|---|---|---|\n| Technology development | Sample production and process scope | Official technology announcements, patents |\n| Trial production | Pilot-line installation and operation | Annual reports, facility disclosures |\n| Customer qualification | Customers conducting evaluations and qualification stage | Earnings releases, official contract disclosures |\n| Mass production | Production capacity and yield stabilization | Quarterly reports, investor-relations materials |\n| Revenue recognition | Revenue and profit from the relevant business | Audit reports, business-unit results |\n\nSome contracts do not disclose customer names. In such cases, revenue growth and utilization rates should be checked together. Orders may not follow even if capital expenditures increase.\n\n## Verification Sequence for Semiconductor Substrate Investments\n\nInvestment reviews should begin with disclosures rather than technical descriptions. A company’s actual exposure must be verified to distinguish a theme from business performance. Materials can be cross-checked in the following order.\n\n1. Find the share of revenue generated by the substrate business in the annual report.\n2. Check whether FC-BGA revenue is separated from general PCB revenue.\n3. Verify the target products and operating schedule for capital investments.\n4. Determine whether customer qualification is in the development, testing, or mass-production stage.\n5. Examine how utilization rates and depreciation expenses affect profitability.\n6. Check customer concentration and inventory changes together.\n7. Cross-check market share against the research firm and reference year.\n\nSamsung Electro-Mechanics and Japanese substrate companies have different business portfolios. It is difficult to compare corporate value based solely on market share. The profit contributions of MLCCs and package substrates must also be separated.\n\nThe same standards are required for glass substrate companies. Possessing pilot facilities alone is insufficient to conclude that a company has a commercial advantage. Verify whether yields and customer qualification status are disclosed.\n\n## Where to Find Official Technical Documents\n\nOfficial technical descriptions of glass substrates can be found in Intel Newsroom’s official announcement. The TSMC 3DFabric technology page covers chiplet and interposer structures. Information on CPO and silicon photonics is available on NVIDIA’s technology pages.\n\nInvestment amounts and mass-production schedules for each company may continue to change. The company’s annual reports and stock-exchange disclosures should be checked first. Brokerage forecasts should be read separately from the company’s confirmed contracts.","content_html":"\u003cp\u003eAI semiconductor substrates are performance-critical components that connect chiplets and HBM while distributing power and signals. FC-BGA and high-layer-count PCBs are already in use, but glass substrates still require validation for mass production. Investment decisions should distinguish technical feasibility from actual revenue.\u003c/p\u003e\n\u003cp\u003eTechnical reference: Intel Newsroom’s announcement on glass substrates; verify the announcement date and subsequent schedules in each company’s latest disclosures\u003c/p\u003e\n\u003ch2\u003e\n\u003ca href=\"#the-role-of-substrates-in-ai-semiconductors\" class=\"anchor\" id=\"the-role-of-substrates-in-ai-semiconductors\"\u003e\u003c/a\u003eThe Role of Substrates in AI Semiconductors\u003c/h2\u003e\n\u003cp\u003eA substrate provides an electrical interconnection network in addition to serving as a board that secures chips. Signal paths and power networks are also formed within the substrate. Package size and wiring density affect system performance.\u003c/p\u003e\n\u003cp\u003eAI accelerators do not consist solely of GPUs or dedicated computing chips. HBM and input/output chiplets are also connected over short distances. Heterogeneous integration combines chips made with different processes into a single package.\u003c/p\u003e\n\u003cp\u003eChiplets are an approach that divides a large monolithic chip into multiple functional blocks. Not all chiplets automatically improve cost or yield. Interface and packaging costs must also be included in the calculation.\u003c/p\u003e\n\u003cp\u003eSubstrates perform the following functions.\u003c/p\u003e\n\u003cul\u003e\n\u003cli\u003eHigh-speed signal connections between chips\u003c/li\u003e\n\u003cli\u003eStable distribution of power and ground\u003c/li\u003e\n\u003cli\u003eSupport for heat-transfer paths from chips\u003c/li\u003e\n\u003cli\u003eConnection of terminals with different sizes and pitches\u003c/li\u003e\n\u003cli\u003eMechanical attachment of the package to the system board\u003c/li\u003e\n\u003c/ul\u003e\n\u003ch2\u003e\n\u003ca href=\"#the-precise-distinction-between-fc-bga-and-abf\" class=\"anchor\" id=\"the-precise-distinction-between-fc-bga-and-abf\"\u003e\u003c/a\u003eThe Precise Distinction Between FC-BGA and ABF\u003c/h2\u003e\n\u003cp\u003eFC-BGA is a package structure widely used for high-performance chips. The chip is connected face-down to the substrate through bumps. Solder balls beneath the substrate connect it to the system board.\u003c/p\u003e\n\u003cp\u003eABF does not mean FC-BGA itself. ABF is a family of build-up insulating materials used in fine wiring layers. Therefore, using FC-BGA and ABF substrate as synonyms in every context is inaccurate.\u003c/p\u003e\n\u003cp\u003eAI packages may require large areas and many input/output connections. Manufacturing becomes more difficult as the number of layers and wiring density increase. However, whether shortages exist varies by period and specification.\u003c/p\u003e\n\u003ch2\u003e\n\u003ca href=\"#comparison-of-high-layer-count-pcbs-and-package-substrates\" class=\"anchor\" id=\"comparison-of-high-layer-count-pcbs-and-package-substrates\"\u003e\u003c/a\u003eComparison of High-Layer-Count PCBs and Package Substrates\u003c/h2\u003e\n\u003cp\u003eThe two types of substrates differ in mounting location and wiring precision. FC-BGA is placed directly beneath the semiconductor die. High-layer-count PCBs connect multiple packages and components at the system level.\u003c/p\u003e\n\u003cdiv class=\"overflow-x-auto\"\u003e\u003ctable\u003e\n\u003cthead\u003e\n\u003ctr\u003e\n\u003cth\u003eCategory\u003c/th\u003e\n\u003cth\u003eFC-BGA Package Substrate\u003c/th\u003e\n\u003cth\u003eHigh-Layer-Count PCB·MLB\u003c/th\u003e\n\u003cth\u003eGlass-Core Substrate·Interposer\u003c/th\u003e\n\u003c/tr\u003e\n\u003c/thead\u003e\n\u003ctbody\u003e\n\u003ctr\u003e\n\u003ctd data-label=\"Category\"\u003ePrimary location\u003c/td\u003e\n\u003ctd data-label=\"FC-BGA Package Substrate\"\u003eBetween the semiconductor die and system board\u003c/td\u003e\n\u003ctd data-label=\"High-Layer-Count PCB·MLB\"\u003eMain board in servers and networking equipment\u003c/td\u003e\n\u003ctd data-label=\"Glass-Core Substrate·Interposer\"\u003eInside the package or in an intermediate interconnection layer\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd data-label=\"Category\"\u003ePrimary role\u003c/td\u003e\n\u003ctd data-label=\"FC-BGA Package Substrate\"\u003eFine-pitch conversion and signal·power connections\u003c/td\u003e\n\u003ctd data-label=\"High-Layer-Count PCB·MLB\"\u003eSystem-level connection of packages and connectors\u003c/td\u003e\n\u003ctd data-label=\"Glass-Core Substrate·Interposer\"\u003eLarge-area fine wiring and dimensional stability\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd data-label=\"Category\"\u003eKey challenges\u003c/td\u003e\n\u003ctd data-label=\"FC-BGA Package Substrate\"\u003eFine wiring, warpage, yield\u003c/td\u003e\n\u003ctd data-label=\"High-Layer-Count PCB·MLB\"\u003eInterlayer alignment, signal loss, drilling\u003c/td\u003e\n\u003ctd data-label=\"Glass-Core Substrate·Interposer\"\u003eBreakage, through-glass vias, metal adhesion, yield\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd data-label=\"Category\"\u003eMarket stage\u003c/td\u003e\n\u003ctd data-label=\"FC-BGA Package Substrate\"\u003eCommercial mass production\u003c/td\u003e\n\u003ctd data-label=\"High-Layer-Count PCB·MLB\"\u003eCommercial mass production\u003c/td\u003e\n\u003ctd data-label=\"Glass-Core Substrate·Interposer\"\u003eDevelopment·trial production·customer qualification coexist\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd data-label=\"Category\"\u003eMetrics to verify\u003c/td\u003e\n\u003ctd data-label=\"FC-BGA Package Substrate\"\u003eProduct specifications and utilization rate\u003c/td\u003e\n\u003ctd data-label=\"High-Layer-Count PCB·MLB\"\u003eShare of revenue from high-layer-count products and customer qualification\u003c/td\u003e\n\u003ctd data-label=\"Glass-Core Substrate·Interposer\"\u003ePilot yield and acquisition of mass-production customers\u003c/td\u003e\n\u003c/tr\u003e\n\u003c/tbody\u003e\n\u003c/table\u003e\u003c/div\u003e\n\u003cp\u003eMLB is a broad term referring to multilayer printed circuit boards. Not every MLB is a high-value-added product for AI servers. It is also difficult to assess product complexity and profitability based solely on the number of layers.\u003c/p\u003e\n\u003cp\u003eFor high-speed signals, materials and stack-up structures work together. Insertion loss and impedance control must also be examined. Connectors and via structures also affect overall performance.\u003c/p\u003e\n\u003ch2\u003e\n\u003ca href=\"#the-relationship-between-mlcc-and-substrates\" class=\"anchor\" id=\"the-relationship-between-mlcc-and-substrates\"\u003e\u003c/a\u003eThe Relationship Between MLCC and Substrates\u003c/h2\u003e\n\u003cp\u003eMLCC is not a substrate but a passive electronic component. It stores electrical charge to mitigate sudden voltage fluctuations. Around processors, it is used for decoupling and noise suppression.\u003c/p\u003e\n\u003cp\u003eAs AI accelerators consume more power, power-network design becomes more difficult. The required number and specifications of MLCCs vary by product. Demand volume cannot be calculated uniformly based only on improvements in chip performance.\u003c/p\u003e\n\u003cp\u003eWhen assessing potential benefits for MLCC suppliers, the product mix matters more than unit count. Rated voltage and capacitance affect unit prices. Size and temperature characteristics also determine actual adoption.\u003c/p\u003e\n\u003ch2\u003e\n\u003ca href=\"#why-glass-substrates-are-drawing-attention\" class=\"anchor\" id=\"why-glass-substrates-are-drawing-attention\"\u003e\u003c/a\u003eWhy Glass Substrates Are Drawing Attention\u003c/h2\u003e\n\u003cp\u003eGlass may offer advantages in flatness and dimensional stability. Its coefficient of thermal expansion can also be adjusted depending on composition and design. These properties are advantageous for reducing alignment errors in large packages.\u003c/p\u003e\n\u003cp\u003eGlass cores may require through-glass vias. Laser processing and metal-filling processes are used. Microcracks and metal adhesion affect yield.\u003c/p\u003e\n\u003cp\u003eGlass does not always provide better heat dissipation than plastic. Thermal performance depends on the material’s thermal conductivity and the overall package structure. Actual cooling is evaluated by including heat sinks and cooling systems.\u003c/p\u003e\n\u003cp\u003eIntel announced glass substrate technology for next-generation advanced packaging, and the announcement date can be verified in Intel Newsroom’s official announcement. This does not mean an immediate industry-wide transition to mass production. Customer qualification and adoption timelines for each company should be verified in the latest disclosures.\u003c/p\u003e\n\u003ch2\u003e\n\u003ca href=\"#conditions-linking-glass-substrates-and-optical-communications\" class=\"anchor\" id=\"conditions-linking-glass-substrates-and-optical-communications\"\u003e\u003c/a\u003eConditions Linking Glass Substrates and Optical Communications\u003c/h2\u003e\n\u003cp\u003eGlass substrates and CPO may be related, but the relationship is not essential. CPO is a technology that places optical engines close to switch chips. Its purpose is to reduce the distance and power issues of copper interconnections.\u003c/p\u003e\n\u003cp\u003eThe mere fact that glass is transparent does not reduce optical loss. The material and geometry of the optical waveguide determine signal loss. Coupling structures and wavelength characteristics must also be designed separately.\u003c/p\u003e\n\u003cp\u003eCPO can also be implemented with silicon photonics and organic substrates. Glass substrates are one potential future integration option. Treating the commercialization schedules of the two technologies as one leads to errors.\u003c/p\u003e\n\u003ch2\u003e\n\u003ca href=\"#substrate-selection-by-requirement\" class=\"anchor\" id=\"substrate-selection-by-requirement\"\u003e\u003c/a\u003eSubstrate Selection by Requirement\u003c/h2\u003e\n\u003cp\u003eSubstrate selection varies depending on package size and input/output density. No single material will replace every AI system. Cost and existing production facilities are also adoption criteria.\u003c/p\u003e\n\u003cdiv class=\"overflow-x-auto\"\u003e\u003ctable\u003e\n\u003cthead\u003e\n\u003ctr\u003e\n\u003cth\u003eRequired condition\u003c/th\u003e\n\u003cth\u003eTechnology considered first\u003c/th\u003e\n\u003cth\u003eRationale\u003c/th\u003e\n\u003c/tr\u003e\n\u003c/thead\u003e\n\u003ctbody\u003e\n\u003ctr\u003e\n\u003ctd data-label=\"Required condition\"\u003eHigh-performance processor packaging\u003c/td\u003e\n\u003ctd data-label=\"Technology considered first\"\u003eFC-BGA\u003c/td\u003e\n\u003ctd data-label=\"Rationale\"\u003eSuitable for fine wiring and input/output connections\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd data-label=\"Required condition\"\u003eSystem-level connection of multiple packages\u003c/td\u003e\n\u003ctd data-label=\"Technology considered first\"\u003eHigh-layer-count PCB\u003c/td\u003e\n\u003ctd data-label=\"Rationale\"\u003eHandles board-level interconnections and power distribution\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd data-label=\"Required condition\"\u003eUltra-fine connections between chiplets\u003c/td\u003e\n\u003ctd data-label=\"Technology considered first\"\u003eSilicon interposer or high-density bridge\u003c/td\u003e\n\u003ctd data-label=\"Rationale\"\u003eEnables short, dense wiring\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd data-label=\"Required condition\"\u003eDimensional stability in large packages\u003c/td\u003e\n\u003ctd data-label=\"Technology considered first\"\u003eConsider glass-core substrates\u003c/td\u003e\n\u003ctd data-label=\"Rationale\"\u003eCan utilize flatness and thermal expansion properties\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd data-label=\"Required condition\"\u003eIntegration of short-range optical input/output\u003c/td\u003e\n\u003ctd data-label=\"Technology considered first\"\u003eCPO and optical waveguide technology\u003c/td\u003e\n\u003ctd data-label=\"Rationale\"\u003eCan reduce electrical interconnection distances\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd data-label=\"Required condition\"\u003eSuppression of voltage fluctuations\u003c/td\u003e\n\u003ctd data-label=\"Technology considered first\"\u003eMLCC and power-management circuits\u003c/td\u003e\n\u003ctd data-label=\"Rationale\"\u003eProvide instantaneous current and mitigate noise\u003c/td\u003e\n\u003c/tr\u003e\n\u003c/tbody\u003e\n\u003c/table\u003e\u003c/div\u003e\n\u003ch2\u003e\n\u003ca href=\"#example-of-signal-path-calculation\" class=\"anchor\" id=\"example-of-signal-path-calculation\"\u003e\u003c/a\u003eExample of Signal-Path Calculation\u003c/h2\u003e\n\u003cp\u003ePackage performance can be assessed by dividing it into the entire signal path. For example, multiple interconnection segments exist between a GPU and HBM. Improving only one segment may leave the overall bottleneck unresolved.\u003c/p\u003e\n\u003col\u003e\n\u003cli\u003eCheck the bump connections between the GPU and HBM.\u003c/li\u003e\n\u003cli\u003eCheck the wiring structure of the interposer or bridge.\u003c/li\u003e\n\u003cli\u003eDistinguish the signal layers from the power layers in the package substrate.\u003c/li\u003e\n\u003cli\u003eCheck the connections between the solder balls and high-layer-count PCB.\u003c/li\u003e\n\u003cli\u003eAdd up losses through the connectors and network optical modules.\u003c/li\u003e\n\u003c/ol\u003e\n\u003cp\u003eNo common fixed values can be applied to this example. This is because wiring lengths and data rates differ by product. Calculations require the vendor’s design rules and measurement results.\u003c/p\u003e\n\u003ch2\u003e\n\u003ca href=\"#common-mistakes-and-misconceptions\" class=\"anchor\" id=\"common-mistakes-and-misconceptions\"\u003e\u003c/a\u003eCommon Mistakes and Misconceptions\u003c/h2\u003e\n\u003cp\u003eA frequent mistake is treating technological direction and investment performance as the same thing. Profitability may deteriorate even as technology adoption increases. In the early stages, depreciation and low yields raise costs.\u003c/p\u003e\n\u003cul\u003e\n\u003cli\u003eTreating FC-BGA and ABF as complete synonyms.\u003c/li\u003e\n\u003cli\u003eInterpreting every MLB as being for AI servers.\u003c/li\u003e\n\u003cli\u003eAssuming the number of MLCCs installed is the same in every AI accelerator.\u003c/li\u003e\n\u003cli\u003eAssuming glass always has better heat-dissipation performance than organic materials.\u003c/li\u003e\n\u003cli\u003eConcluding that optical communications will adopt glass based solely on its transparency.\u003c/li\u003e\n\u003cli\u003eInterpreting a development announcement as customer qualification or mass-production revenue.\u003c/li\u003e\n\u003cli\u003eFailing to verify the survey date and scope of market-share figures.\u003c/li\u003e\n\u003c/ul\u003e\n\u003cp\u003eA specific company’s market share may vary by research firm. Classification criteria for AI server applications are also not standardized. Figures without sources and reference years are difficult to use as an investment basis.\u003c/p\u003e\n\u003ch2\u003e\n\u003ca href=\"#metrics-for-verifying-companies-and-industries\" class=\"anchor\" id=\"metrics-for-verifying-companies-and-industries\"\u003e\u003c/a\u003eMetrics for Verifying Companies and Industries\u003c/h2\u003e\n\u003cp\u003eCompanies involved in glass substrates should be evaluated by production stage. Research and development and pilot production differ from mass production. Mass-production facilities also do not guarantee customer revenue.\u003c/p\u003e\n\u003cdiv class=\"overflow-x-auto\"\u003e\u003ctable\u003e\n\u003cthead\u003e\n\u003ctr\u003e\n\u003cth\u003eVerification stage\u003c/th\u003e\n\u003cth\u003eFacts to verify\u003c/th\u003e\n\u003cth\u003eDocuments to check\u003c/th\u003e\n\u003c/tr\u003e\n\u003c/thead\u003e\n\u003ctbody\u003e\n\u003ctr\u003e\n\u003ctd data-label=\"Verification stage\"\u003eTechnology development\u003c/td\u003e\n\u003ctd data-label=\"Facts to verify\"\u003eSample production and process scope\u003c/td\u003e\n\u003ctd data-label=\"Documents to check\"\u003eOfficial technology announcements, patents\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd data-label=\"Verification stage\"\u003eTrial production\u003c/td\u003e\n\u003ctd data-label=\"Facts to verify\"\u003ePilot-line installation and operation\u003c/td\u003e\n\u003ctd data-label=\"Documents to check\"\u003eAnnual reports, facility disclosures\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd data-label=\"Verification stage\"\u003eCustomer qualification\u003c/td\u003e\n\u003ctd data-label=\"Facts to verify\"\u003eCustomers conducting evaluations and qualification stage\u003c/td\u003e\n\u003ctd data-label=\"Documents to check\"\u003eEarnings releases, official contract disclosures\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd data-label=\"Verification stage\"\u003eMass production\u003c/td\u003e\n\u003ctd data-label=\"Facts to verify\"\u003eProduction capacity and yield stabilization\u003c/td\u003e\n\u003ctd data-label=\"Documents to check\"\u003eQuarterly reports, investor-relations materials\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd data-label=\"Verification stage\"\u003eRevenue recognition\u003c/td\u003e\n\u003ctd data-label=\"Facts to verify\"\u003eRevenue and profit from the relevant business\u003c/td\u003e\n\u003ctd data-label=\"Documents to check\"\u003eAudit reports, business-unit results\u003c/td\u003e\n\u003c/tr\u003e\n\u003c/tbody\u003e\n\u003c/table\u003e\u003c/div\u003e\n\u003cp\u003eSome contracts do not disclose customer names. In such cases, revenue growth and utilization rates should be checked together. Orders may not follow even if capital expenditures increase.\u003c/p\u003e\n\u003ch2\u003e\n\u003ca href=\"#verification-sequence-for-semiconductor-substrate-investments\" class=\"anchor\" id=\"verification-sequence-for-semiconductor-substrate-investments\"\u003e\u003c/a\u003eVerification Sequence for Semiconductor Substrate Investments\u003c/h2\u003e\n\u003cp\u003eInvestment reviews should begin with disclosures rather than technical descriptions. A company’s actual exposure must be verified to distinguish a theme from business performance. Materials can be cross-checked in the following order.\u003c/p\u003e\n\u003col\u003e\n\u003cli\u003eFind the share of revenue generated by the substrate business in the annual report.\u003c/li\u003e\n\u003cli\u003eCheck whether FC-BGA revenue is separated from general PCB revenue.\u003c/li\u003e\n\u003cli\u003eVerify the target products and operating schedule for capital investments.\u003c/li\u003e\n\u003cli\u003eDetermine whether customer qualification is in the development, testing, or mass-production stage.\u003c/li\u003e\n\u003cli\u003eExamine how utilization rates and depreciation expenses affect profitability.\u003c/li\u003e\n\u003cli\u003eCheck customer concentration and inventory changes together.\u003c/li\u003e\n\u003cli\u003eCross-check market share against the research firm and reference year.\u003c/li\u003e\n\u003c/ol\u003e\n\u003cp\u003eSamsung Electro-Mechanics and Japanese substrate companies have different business portfolios. It is difficult to compare corporate value based solely on market share. The profit contributions of MLCCs and package substrates must also be separated.\u003c/p\u003e\n\u003cp\u003eThe same standards are required for glass substrate companies. Possessing pilot facilities alone is insufficient to conclude that a company has a commercial advantage. Verify whether yields and customer qualification status are disclosed.\u003c/p\u003e\n\u003ch2\u003e\n\u003ca href=\"#where-to-find-official-technical-documents\" class=\"anchor\" id=\"where-to-find-official-technical-documents\"\u003e\u003c/a\u003eWhere to Find Official Technical Documents\u003c/h2\u003e\n\u003cp\u003eOfficial technical descriptions of glass substrates can be found in Intel Newsroom’s official announcement. The TSMC 3DFabric technology page covers chiplet and interposer structures. Information on CPO and silicon photonics is available on NVIDIA’s technology pages.\u003c/p\u003e\n\u003cp\u003eInvestment amounts and mass-production schedules for each company may continue to change. The company’s annual reports and stock-exchange disclosures should be checked first. Brokerage forecasts should be read separately from the company’s confirmed contracts.\u003c/p\u003e\n","tags":["Semiconductors","AI Data Center","AI chips","HBM","Technology strategy","Glass substrate"],"faqs":[{"question":"Do FC-BGA and ABF substrate mean the same thing?","answer":"They do not mean exactly the same thing. FC-BGA is a package structure that uses flip-chip technology and solder balls, while ABF is a family of insulating materials primarily used for the substrate's fine wiring layers."},{"question":"How do high-layer-count PCBs differ from semiconductor package substrates?","answer":"A package substrate converts fine pitches directly beneath the semiconductor die. A high-layer-count PCB connects multiple components, such as packages, memory, and connectors, at the system level."},{"question":"Will glass substrates replace all conventional organic substrates?","answer":"It has not been confirmed that they will fully replace them. Glass offers advantages in flatness and dimensional stability, but challenges remain in breakage, through-glass via fabrication, metal adhesion, cost, and yield."},{"question":"Do glass substrates have better heat dissipation performance?","answer":"Not always. Heat dissipation must be evaluated based on the entire structure, including the die, adhesive layer, heat sink, and cooling system, rather than solely on the material's thermal conductivity."},{"question":"Is a glass substrate essential for implementing CPO?","answer":"It is not a requirement. CPO can also be implemented using silicon photonics and conventional packaging technologies, while glass substrates are an option that could be used to integrate optical waveguides in the future."},{"question":"Do AI accelerators always contain thousands of MLCCs?","answer":"The quantity varies by product, so a fixed number cannot be applied. The required quantity and specifications vary depending on the power architecture, package size, capacitance, and placement method."},{"question":"How can the mass-production potential of a glass substrate company be assessed?","answer":"The pilot line, customer qualification, production capacity, yield, utilization rate, and revenue contribution must be assessed at each stage. Mass-production revenue should not be assumed based solely on a development announcement or equipment installation."},{"question":"Is the shortage of FC-BGA supply an ongoing structural phenomenon?","answer":"It cannot be assumed to persist across all specifications. Supply conditions vary depending on package size, wiring complexity, customer qualification, the timing of capacity expansion, and end demand."}],"sources":[{"url":"https://www.intel.com/content/www/us/en/newsroom/news/intel-unveils-industry-first-glass-substrates.html","title":"Intel Unveils Industry-First Glass Substrates to Meet Demand for More Powerful Compute","type":"source"},{"url":"https://3dfabric.tsmc.com/","title":"TSMC 3DFabric","type":"source"},{"url":"https://www.ibm.com/think/topics/chiplet","title":"What Is a Chiplet?","type":"source"}],"images":[{"id":1148,"url":"https://injoys.com/rails/active_storage/blobs/proxy/eyJfcmFpbHMiOnsiZGF0YSI6MTYyMjAsInB1ciI6ImJsb2JfaWQifX0=--ab5c8e230787c7d6691f2fc19f05a3a928ed0396/ai-e18c9afe.webp","is_representative":true,"generation_method":"ai_photo","license":"ai_generated","mime_type":"image/webp","translations":{"ko":{"alt":"클린룸에서 대형 투명 반도체 기판을 검사하는 방진복 차림의 작업자","caption":"작업자가 현미경과 모니터를 이용해 유리 반도체 기판의 미세 회로와 결함을 검사하고 있다.","description":null},"en":{"alt":"Cleanroom worker inspecting a large transparent semiconductor substrate under a microscope","caption":"A technician uses a microscope and monitor to inspect the fine circuitry and defects of a glass substrate.","description":null},"ja":{"alt":"クリーンルームで大型の透明な半導体基板を顕微鏡検査する作業員","caption":"作業員が顕微鏡とモニターを使い、ガラス基板の微細回路や欠陥を検査している。","description":null},"es":{"alt":"Técnica inspeccionando un gran sustrato semiconductor transparente en una sala limpia","caption":"Una técnica usa un microscopio y un monitor para revisar los circuitos finos y defectos de un sustrato de vidrio.","description":null},"id":{"alt":"Teknisi memeriksa substrat semikonduktor transparan berukuran besar di ruang bersih","caption":"Teknisi menggunakan mikroskop dan monitor untuk memeriksa sirkuit halus serta cacat pada substrat kaca.","description":null},"pt":{"alt":"Técnica inspecionando um grande substrato semicondutor transparente em uma sala limpa","caption":"Uma técnica usa microscópio e monitor para verificar circuitos finos e defeitos em um substrato de vidro.","description":null},"zh-hant":{"alt":"無塵室技術人員以顯微鏡檢查大型透明半導體基板","caption":"技術人員透過顯微鏡與螢幕檢查玻璃基板上的精細電路和缺陷。","description":null},"de":{"alt":"Technikerin prüft in einem Reinraum ein großes transparentes Halbleitersubstrat","caption":"Eine Technikerin untersucht mit Mikroskop und Monitor die feinen Schaltungen und Defekte eines Glassubstrats.","description":null}}},{"id":1149,"url":"https://injoys.com/rails/active_storage/blobs/proxy/eyJfcmFpbHMiOnsiZGF0YSI6MTYyMzMsInB1ciI6ImJsb2JfaWQifX0=--e0815ebd110ee735efcde353ea96e8aba06e81bd/ai-50153c08.webp","is_representative":false,"generation_method":"ai_image","license":"ai_generated","mime_type":"image/webp","translations":{"ko":{"alt":"다층 유기 기판과 투명 유리기판 기반 AI 반도체 패키지 구조 비교","caption":"칩, 배선, 수직 연결부, 솔더볼로 구성된 두 반도체 기판 구조와 제조·검사 요소를 비교한다.","description":null},"en":{"alt":"Comparison of AI chip packages using a multilayer organic substrate and transparent glass substrate","caption":"The graphic compares two substrate structures with chips, wiring, vertical interconnects, solder balls, and process indicators.","description":null},"ja":{"alt":"多層有機基板と透明ガラス基板を用いたAI半導体パッケージ構造の比較","caption":"チップ、配線、垂直接続、はんだボールを備えた2種類の基板構造と製造・検査要素を比較している。","description":null},"es":{"alt":"Comparación de paquetes de chips de IA con sustrato orgánico multicapa y sustrato de vidrio","caption":"El gráfico compara dos estructuras con chips, cableado, interconexiones verticales, bolas de soldadura e indicadores de proceso.","description":null},"id":{"alt":"Perbandingan paket chip AI dengan substrat organik berlapis dan substrat kaca transparan","caption":"Grafik ini membandingkan dua struktur substrat dengan cip, jalur, koneksi vertikal, bola solder, dan indikator proses.","description":null},"pt":{"alt":"Comparação de pacotes de chips de IA com substrato orgânico multicamada e substrato de vidro","caption":"O gráfico compara duas estruturas com chips, fiação, interconexões verticais, esferas de solda e indicadores de processo.","description":null},"zh-hant":{"alt":"多層有機基板與透明玻璃基板的AI半導體封裝結構比較","caption":"圖中比較兩種基板的晶片、布線、垂直互連、焊球及製程檢測要素。","description":null},"de":{"alt":"Vergleich von KI-Chipgehäusen mit organischem Mehrlagensubstrat und transparentem Glassubstrat","caption":"Die Grafik vergleicht zwei Substrukturen mit Chips, Leiterbahnen, vertikalen Verbindungen, Lötkugeln und Prozessanzeigen.","description":null}}}],"published_at":"2026-09-08T23:39:04+09:00","updated_at":"2026-09-08T23:39:04+09:00","license":"cc_by","translation_status":"reviewed","available_locales":["ko","en","ja","es"],"data_locales":["ko","en","ja","es","id","pt","zh-hant","de"],"url":"https://injoys.com/en/articles/ai-semiconductor-substrate-glass-transition"}